(1) Field of the Invention
The invention relates to a structure for circuit assembly, specifically to such a structure which is used for circuit assembly of a display apparatus.
(2) Description of the Prior Art
Assembly for display normally uses the technology of tape automated bonding (TAB) or of chip on glass bonding (COG), and so on. Compared to TAB, COG uses less amount of flexible circuit boards and printed circuit boards, and thereby can reduce the production cost.
For further reducing the demand of the amount of flexible circuit boards and the layers of printed circuit board to gain more cost benefit, those products using the technology of COG also apply the wiring-on-array (WOA) on array substrate to cascade driver chips. Among the cascaded driver chips, data and control signals are transmitted only to the first driver chip, and thereafter they can be delivered to the other cascaded driver chips. As a result, the amount of wiring on the flexible circuit board and printed circuit board can be reduced, and the cost can be further decreased. Because driver chips are cascaded with the WOA on the array substrate, thereby simplifying the design for printed circuit board and reducing the number of layers of circuit board can lead to further cost down.
Because function of signals on gate drivers is less than those on source drivers, the number of connections required for gate drivers is relatively limited. It thus makes it easier to design the peripheral layout surrounding the display area and the arrangement of bonding pads to the design with cascade. For the cost-down requirement today, an attempt to cascade source drivers has become a dedicated approach field in the panel manufacture. While there are a number of function of signals on the source drivers, the flexibility of design for the peripheral layout will be restricted by the limit of size of a flip-chip; moreover, it has increased the difficulty to be compatible with the present process, such as using the same testing method, module tools, and so on. Therefore, how to improve the design of WOA on the array substrate so as to further reduce the cost of components on panel has become a request to achieve in the panel manufacture.
Refer to FIG. 1A, showing a conventional display. A panel 10 comprises a display area 11, a plurality of source drivers 12, and a plurality of gate drivers 13 disposed at the surrounding of the display area 11. The source drivers 12 and the gate drivers 13 respectively connect with printed circuit boards 17a and printed circuit boards 17b via respective flexible circuit boards 20. As shown in FIG. 1B, on the panel 10, an area 14 between two source drivers, the driver 12a and the driver 12b which are not cascaded but adjacent to each other, only keeps a few of dummy patterns 16 and an alignment structure 15, providing for circuit assembly of the panel 10 and the flexible circuit board 20.
As shown in FIG. 1C, the alignment structure 15 includes an alignment mark 151. While assembling the panel 10 and the flexible circuit board 20, a positional alignment is examined for the board 20 though a transmissive area 21 which is light-transmissive and the alignment mark 151 on the panel 10. If the alignment mark 151 is properly positioned inside the transmissive area 21, the pads 121 the from source driver 12 are aligned to leads 22 of the flexible circuit board 20. As shown in FIG. 1D, while the location of the transmissive area 21 shifts from that of the mark 151, this means that the location of the pad 121 also shifts from that of the lead 22. However, the degree of assembly shift is not very clear for visual check.
As shown from the layout design in the figure, the edge of every panel 10 is required to keep the alignment mark 151 during a bonding process. Because these alignment marks 151 are located between two drivers and their positions can not be changed arbitrarily under the limitation of manufacturing tools, the space between every two adjacent leads of the drivers can not be effectively utilized for constructing prospective wiring. In particular, the demand in increasing number of contacts for the source drivers can't be met and thereby the pattern design with the WOA on array substrate is greatly limited.